1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having fine pattern electrode structure, such as electrode structure of a high-frequency silicon transistor, for example.
2. Description of the Prior Art
FIGS. 1 to 8 are sectional views showing a conventional method of fabricating a high-frequency silicon transistor, respectively.
First, a P-type guard ring layer 2, a P-type base junction region 3 and an N-type emitter junction region 4 are formed on an N-type epitaxial layer 1 through a well-known impurity diffusion technique, as shown in FIG. 1. Numeral 5 denotes an insulating layer, which is formed by an oxide film through thermal oxidation. In this case, the N-type epitaxial layer 1 serves as a collector region. The guard ring layer 2 is adapted to increase the so-called V.sub.CBO breakdown voltage when reverse voltage is applied across the collector and the base. In general, this guard ring layer 2 is formed simultaneously with the base junction region 3 by providing an oxide film (part of the insulating layer 5) on a prescribed region of the N-type epitaxial layer 1 and selectively diffusing a P-type impurity into an upper layer part of the epitaxial layer 1 through the oxide film, which serves as a mask. In a similar manner, another oxide film (remaining part of the insulating layer 5) is formed on another prescribed region of the chip to cover the said oxide film and an N-type impurity is selectively diffused into an upper layer part of the base junction region 3 through the oxide film, which serves as a mask, to thereby form the emitter junction region 4. Consequently, a concave step portion 7 is defined in a section of the insulating layer 5 corresponding to the guard ring layer 2 within a non-electric forming region 6 shown in FIG. 1.
On the other hand, the insulating layer 5 is provided with a contact hole 9 in a position corresponding to the emitter junction region 4 for extracting an emitter electrode and with another contact hole 10 in a position corresponding to the base junction region 3 for extracting a base electrode, within an electrode forming region 8 shown in FIG. 1. In the case of the high-frequency silicon transistor, an opening portion of the insulating layer 5 defined in formation of the emitter junction region 4 is generally employed as the contact hole 9. Platinum silicide layers 11 and 12 are formed in the contact holes 9 and 10 respectively, in order to attain low ohmic contact resistance.
Then, a barrier metal layer 13 having substantially uniform thickness is formed on the chip to cover the insulating layer 5, as shown in FIG. 2. Further, a conductive thin film 14 of gold is formed on the barrier metal layer 13 by sputtering. In general, the thickness of the conductive thin film 14 is about 1000 .ANG..
Thereafter a photoresist film 15 is formed on a prescribed region of the conductive thin film 14 to serve as a mask for selectively forming an emitter electrode 16 and a base electrode 17 within the electrode forming region 8 respectively by electrolytic plating, as shown in FIG. 3. At this time, the conductive thin film 14 is adapted to effectively retain current flow in the electrolytic plating process. Further, the barrier metal layer 13 is adapted to prevent the semiconductor layer from intrusion of metal material atoms forming the electrodes 16 and 17 and the conductive thin film 14.
Then, the spent photoresist film 15 is removed as shown in FIG. 4.
Thereafter the electrodes 16 and 17 are utilized as masks to selectively remove the conductive thin film 14 by anisotropic etching such as sputter etching, for example, hardly causing side etching, as shown in FIG. 5. In the case of the high-frequency transistor, refinement of electrode patterns generally progresses with increase in frequency. Consequently, the electrodes 16 and 17 are reduced in width such that electrode separation or V.sub.EBF failure (degradation of voltage characteristics with respect to emitter-to-base forward voltage) is caused by slight side etching in electrode portions of the conductive thin film 14. Therefore, the conductive thin film 14 cannot be removed by isotropic etching which causes side etching, but is removed by anisotropic etching which hardly causes side etching.
As the result, a part 14a of the conductive thin film 14 is left in a concave step portion 18 of the barrier metal layer 13 located above the guard ring layer 2, as shown in FIG. 5. That is, the part 14a of the conductive film 14 is inevitably left when the conductive thin film 14 having thickness W is removed by anisotropic etching as shown in FIG. 6, which is an enlarged sectional view of a part A shown in FIG. 5.
If the barrier metal layer 13 is thereafter selectively removed by etching through the electrodes 16 and 17 serving as masks as shown in FIG. 7, therefore, the following problem is caused: Since the thickness W of the conductive thin film 14 is small and the concave step portion 7 of the insulating layer 5 has small depth of not more than 0.5 .mu.m, a masking effect by the part 14a of the conductive thin film 14 is so reduced that the barrier metal layer 13 is side-etched at the concave step portion 7. Consequently, the part 14a of the conductive thin film 14 is barely left on the concave step portion 7 of the insulating layer 5 as shown in FIG. 7, or the part 14a of the conductive thin film 14 is separated to cross the base electrode 17 and the emitter electrode 16 extending in the form of stripes as shown in FIG. 8, to cause shorting across the emitter and the base.